module top (
    input clk,
    input rst,
    input [15:0] sw,
    input ps2_clk,
    input ps2_data,
    input [4:0] button,
    output [15:0] ledr,
    output VGA_CLK,
    output VGA_HSYNC,
    output VGA_VSYNC,
    output VGA_BLANK_N,
    output [7:0] VGA_R,
    output [7:0] VGA_G,
    output [7:0] VGA_B,
    output [7:0] seg0,
    output [7:0] seg1,
    output [7:0] seg2,
    output [7:0] seg3,
    output [7:0] seg4,
    output [7:0] seg5,
    output [7:0] seg6,
    output [7:0] seg7
);

// ALU
wire [3:0] num;
alu alu_1(
  .in_x(sw[3:0]),
  .in_y(sw[7:4]),
  .sel(sw[15:13]),
  .out_s(num[3:0])
);
assign ledr[7:0] = sw[7:0];
assign ledr[11:8] = num[3:0];
assign ledr[15:13] = sw[15:13];
bcd7segsign bcd7seg_1(
	.b(num[3:0]),
	.h(seg0[7:1]),
	.sign(seg1[7:1])
);
bcd7segsign bcd7seg_2(
	.b(sw[3:0]),
	.h(seg6[7:1]),
	.sign(seg7[7:1])
);
bcd7segsign bcd7seg_3(
	.b(sw[7:4]),
	.h(seg3[7:1]),
	.sign(seg4[7:1])
);
// 关闭无关的数码管
assign seg2 = 8'b11111111;
assign seg5 = 8'b11111111;
endmodule
